1. Field of the Invention
This invention relates to a semiconductor memory device, and particularly to a dynamic random access memory (DRAM) having a memory cell array of a split-operation mode.
2. Description of the Related Art
The following example has heretofore been known as a technique employed in such a field.
FIG. 3 is a view showing the configuration of a conventional semiconductor memory device of a block-splitting mode. FIG. 4 is an enlarged view of an A portion shown in FIG. 3. FIG. 5 is a view illustrating a sense amplifier train of the conventional semiconductor memory device shown in FIG. 3.
In general, a large-capacity DRAM has a memory array provided so as to be divided into four sub-array regions by X decoders and Y decoders. Sub-array regions 10 and 11 are disposed on the upper half side of a chip, whereas sub-array regions 12 and 13 are disposed on the lower half side of the chip. X decoders are respectively disposed within regions 14 defined between the two. The sub-array regions 10 and 13 are disposed on the left half side of the chip and the sub-array regions 11 and 12 are disposed on the right half side of the chip. Y decoders are respectively disposed within regions 15 defined between the two. Each of the sub-array regions comprises a plurality of cell array regions 23. A plurality of memory cells, a plurality of bit line pairs 26 and a plurality of word lines are disposed within each of the cell array regions 23.
As shown in FIG. 5, sense amplifier trains 24 each composed of a plurality of sense amplifier circuits 21 and a sense latch circuit 22 are respectively provided on both sides of the respective cell array regions 23 of the sub-array regions as seen in the left and right directions. Incidentally, each sense latch circuit 22 has an NMOS transistor 22A and a PMOS transistor 22B. The gates of both transistors are respectively controlled by sense latch signals 25 each having a positive phase and an opposite phase.
Source wires or interconnections 16, 17, 18 and 19 respectively electrically connected to the plurality of sense amplifier trains 24 are disposed so as to surround the sub-array regions. The source interconnections 16 and 17 are principally used for the plurality of sense amplifier trains 24 in the sub-array regions 10 and 11 provided on the upper half side of the chip, whereas the source interconnections 18 and 19 are principally used for the plurality of sense amplifier trains 24 in the sub-array regions 12 and 13 provided on the lower half side of the chip.
When the four sub-array regions 10, 11, 12 and 13 are divisionally operated, the sub-array regions 10 and 11 on the upper half side have heretofore been activated simultaneously as blocks A and the sub-array regions 12 and 13 on the lower half side have heretofore been activated simultaneously as blocks B in timing different from that for the blocks A. In the way of such block division or splitting, however, circuits used as noise sources have been biased toward upper or lower power sources.
Namely, when each block A is activated (i.e., when memory cells in the block A are selected), a plurality of cell arrays of each of the sub-array regions 10 and 11 are simultaneously activated (selected) and the sense amplifier trains 24 on both sides thereof are also activated (a sense latch operation is performed). When the PMOS transistor 22B and the NMOS transistor 22A are turned on so that a source interconnection supplied with a power source potential Vdd (e.g., 5V) and its corresponding sense amplifiers SA are electrically connected to one another and a source interconnection supplied with a ground potential Gnd (e.g., 0V) and its corresponding sense amplifiers SA are electrically connected to one another, each sense amplifier train 24 is activated as shown in FIG. 6.
When each sense amplifiers SA is activated, electric charges are charged or discharged between the source interconnections and each sense amplifier SA to amplify information stored in each memory cell, which has been transferred to each bit line pair 26 (the arrows show the manner of charge or discharge).
However, since the plurality of activated sense amplifier trains 24 are biased toward the source interconnections 16 and 17 as shown in FIG. 7, high noise occurs in the source interconnections 16 and 17 (since the blocks B are not activated on the other hand, no noise is produced in the source interconnections 18 and 19). The speed of amplifying information by each sense amplifier SA becomes slow under the influence of the noise and the semiconductor memory device will eventually lead to a slow operating speed. Therefore, there has been a demand for the improvement in the operating speed of the semiconductor memory device.